1. Field of the Invention
This invention relates to a circuit board having a heating means and a hermetically sealed multi-chip package.
2. Related Art
Recently, a wide variety of smaller and lighter mobile electronic devices have been developed. Such mobile electronic devices include cellular phones, digital video/still cameras, PDAs (Personal Digital Assistants), HPCs (Handheld Personal Computers), MP3 (MPEG-1 Audio Layer-3) players and notebook computers. Semiconductor packages that include semiconductor devices (or chips) are typically mounted within these mobile electronic devices. To fit inside of a small mobile electronic device, the size of the semiconductor packages must be approximately equal to the size of the semiconductor chips that are housed within the semiconductor packages.
This CSP (Chip Size Package or Chip Scale Package), which is a package that is approximately the equal to the size of the semiconductor chips that are housed within the package, was developed in 1990s. In particular, the CSP was introduced in the semiconductor packaging industry in 1992. Since then, various types of CSPs have been developed by LSI manufacturers. The most popular CSP is the Fine pitch Ball Grid Array (FBGA), which is widely used for memory and logic chips. In addition, Bump Chip Carrier (BCC), Face Down-FBGA (FD-FBGA), Super-CSP, and Fine pitch Land Grid Array (FLGA) packages have been developed.
In a CSP, the reliability of its solder joints is one of most important technical issues. To evaluate CSPs, thermal cycling tests and mechanical strength tests are used. CSPs are mounted to a circuit board via solder balls or solder bumps, and hence CSP solder joints can be viewed as solder joints of flip-chip devices. The reliability of the solder joints in flip-chip and CSP assemblies is strongly affected by the following conditions:                (1) CSPs are leadless and, with a few exceptions, their assemblies do not have much compliance built-in. Compliancy helps relieve solder joint stresses as shown with packages having tall leads.        (2) Their effective coefficient of thermal expansion (CTE) tends to be low because of high silicon content. Many CSPs are not well CTE-matched to organic boards.        (3) Assembled packages feature a low standoff for miniaturization purposes. This factor increases cyclic strains in solder joints.        (4) Flip chip and CSP solder joints have smaller load bearing or crack propagation areas than conventional assemblies, implying higher stresses and shorter crack propagation times.        (5) Flip chip assemblies also suffer from competing failure modes, such as die cracking and underfill delamination.        
The above concerns are supported by thermal cycling results, which suggest that many flip chip and CSP assemblies are less reliable than Plastic Ball Grid Arrays (PBGAs). For example, PBGAs on FR4 boast a median life of 5,000-10,000 cycles during thermal cycling between 0° C. and 100° C. Under similar conditions, most CSP assemblies offer median lives in the range of 1,000-5,000 cycles, with some as low as 5-100 cycles.
The poor reliability of the solder joint of CSPs is primarily due to the small size of its solder joints. For identical chips in flip-chip/CSP or BGA formats, the joint-to-height ratio ranges from about 1:5 to 1:6, which implies that shear strains in flip-chip/CSP solder joints are perhaps 6.25 times higher than in BGA assemblies. Using the Coffin-Manson relationship for solder joint life estimates, the strain ratio results in a fatigue life ratio of about 40. Furthermore, the ability to absorb energy of solder joints in flip-chip/CSPs is less than that of the BGA package.
U.S. Pat. No. 5,396,403, which is assigned to Hewlett-Packard Company and is entitled “Heat Sink Assembly with Thermally-Conductive Plate for a Plurality of Integrated Circuits on a Substrate,” discloses an improved structure for heat dissipation in a multi-chip module (MCM) device where a number of chips are mounted via solder balls without imposing mechanical stress.
FIG. 1 shows the conventional heat dissipation structure disclosed in U.S. Pat. No. 5,396,403. The conventional MCM heat dissipation structure includes a substrate 1 that has one or more chips 2 on an upper surface 3 and more chips 5 on a lower surface 6. The upper chips 2 are thermally coupled to a first thermally conductive plate 7 through a first thermal interface 8. The first plate 7 is thermally coupled to a first heat sink 10 through a second thermal interface 9. Similarly, the lower chips 5 are thermally coupled to a second thermally conductive plate 11 through a third thermal interface 12, and the second plate 11 is thermally coupled to a second heat sink 13 through a fourth thermal interface 14.
The first and second heat sinks 10 and 13 enclose the MCM and the two thermally conductive plates 7 and 11 in a cavity 15. The heat sinks 10 and 13 are mechanically fastened together by screws or other fasteners. A flat cable 16 extends between the heat sinks to establish electrical connections with external circuitry.
In this conventional MCM heat dissipation structure, the heat sink assembly provides an efficient, thermally conductive path between the chips in the MCM and the heat sinks in the MCM. Further, mechanical stresses from lateral chip motion resulting from thermal effects, such as differential expansion are minimized and other mechanical stresses are eliminated.
However, as CSP and flip chips are miniaturized, the solder joints become increasingly smaller, which increases the need for improving and enhancing the reliability of the solder joints.